semiconductor technical data order number: mpc9990/d rev 5, 03/2002 motorola advanced clock drivers device data 287 the mpc9990 is a low voltage pll clock driver designed for high speed clock generation and distribution in high performance computer, workstation and server applications . the clock driver acc epts a lvpecl compatible clock signal and provides 10 low skew, differential hstl 1 compatible out- puts, one hstl compatible output for system synchronization purposes and one hstl compatible pll feedback output. the device operates from a dual voltage supply: 3.3 v for the core logic and 1.8 v for the hstl outputs. the fully integrated pll supports an input frequency range of 75 to 287.5 mhz. the output frequencies are configurable. ? supports high performance hstl clock distribution systems ? compatible to ia64 processor systems ? fully integrated pll, differential design ? core logic operates from 3.3 v power supply ? hstl outputs operate from a 1.8 v supply ? programmable frequency by output bank ? 10 hstl compatible outputs (two banks) ? hstl compatible pll feedback output ? hstl compatible sychronization output (qsync) ? max. skew of 80 ps within output bank ? zero?delay capability: max. spo (tpd) window of 150 ps ? lvpecl compatible clock input, lvcmos compatible control inputs ? temperature range of 0 to +70 c the mpc9990 provides output clock frequencies required for high?performance computer system optimization. the device drives up to 10 dif ferential clock loads within the frequency range of 75 to 287.5 mhz. the 10 outputs are organized in 2 banks of 3 and 7 differential outputs. in the standard configuration the qfb output pair is connected to the fb input pair closing the p ll loop and enabling zero delay operation from the clk input to the outputs. bank b outputs are frequency and phase aligned to the clk input, providing exact copies of the high?speed input signal. bank a outputs are configured to operate at slower speeds driving the system bus devices. the output frequency ratio of bank a to bank b is adjustable (for available ratios, see ?mpc999 0 application: cpu to system bus frequency ratios? on page 288) for system optimization. in a computer application, bank b outputs generate the clock signals for the devices operating at the cpu frequency, while bank a outputs are configured to drive the clock signals for the devices running at lower speeds (system clock). four individual frequency ratios are available, provi ding a high degree of flexibility. the frequency ratios between cpu clock and system clock provided by the mpc9990 are listed in the table ?output configuration? on page 290. the qsync output functionality is designed for system synchronization purpose. qsync is asserted at coincident rising edges of cpu (bank b and qfb signal) and slower system clock (bank a) outputs (see ?qsync phase relation diagram? on page 290), providing baseline timing in systems with fractional clocks. the qsync output is asserted for one qfb high pulse, centered on the rising qfb output. figure 1. mpc9990 application example 1. in order to minimize output?to?output skew, hstl outputs of the mpc9990 are generated with an open emitter architecture. for output termina- tion, see ?hstl output termination and ac test reference? on page 291. this document contains information on a product under development. motorola reserves the right to change or discontinue this pr oduct without notice. 2 low voltage differential pecl?hstl pll clock driver fa suffix 48?lead lqfp package case 932 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 288 figure 2. mpc9990 logic diagram table 1: mpc9990 application: cpu to system bus frequency ratios qa to qb frequency ratio 1:1 1:2 3:4 4:5 output frequencies for clk = 75 mhz (bsel=1, vco_sel=1) qa output frequency 75 37.5 56.25 60 mhz qb output frequency 75 75 75 75 mhz output frequencies for clk = 100 mhz (bsel=1, vco_sel=1) qa output frequency 100 50 75 80 mhz qb output frequency 100 100 100 100 mhz output frequencies for clk = 125 mhz (bsel=1, vco_sel=1) qa output frequency 125 62.5 93.75 100 mhz qb output frequency 125 125 125 125 mhz output frequencies for clk = 150 mhz (bsel=1, vco_sel=0) qa output frequency 150 75 112.5 120 mhz qb output frequency 150 150 150 150 mhz output frequencies for clk = 200 mhz (bsel=1, vco_sel=0) qa output frequency 200 100 150 160 mhz qb output frequency 200 200 200 200 mhz output frequencies for clk = 250 mhz (bsel=1 vco_sel=0) qa output frequency 250 125 187.5 200 mhz qb output frequency 250 250 250 250 mhz 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 289 mpc9990 figure 3. 48?lead package pinout (top view) table 2: pin configuration pin i/o type internal resistor description clk, clk input lvpecl clk: pull-down, clk : pull-up differential clock frequency input fb, fb input hstll fb: pull-down, fb : pull-up differential feedback input qan, qan output hstl bank a outputs qbn, qbn output hstl bank b outputs qsync, qsync output hstl synchronization output qfb, qfb output hstl differential feedback output vco_sel input lvcmos pull-down selection of operating frequency range asel[0:1] input lvcmos pull-down selection of bank a output frequency bsel input lvcmos pull-down selection of bank b output frequency test input lvcmos pull-down selection of pll operation or test mode (pll bypass) mr input lvcmos pull-up master reset. assertion of master reset required on startup oe input lvcmos pull-up output enable v cca power supply analog power supply, typical 3.3 v v cc power supply core power supply, typical 3.3 v v cco power supply output power supply, typical 1.8 v gnd ground output, analog and core logic ground, 0v (vee) 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 290 table 3: output frequency relationship for an example configuration asel[0] asel[1] bsel f qan f qbn f qfb qsync 0 0 0 clk clk clk l 0 1 0 clk 2 clk 2 clk enabled 1 0 0 clk x 3 4 clk x 3 4 clk enabled 1 1 0 clk x 4 5 clk x 4 5 clk enabled 0 0 1 clk clk clk l 0 1 1 clk 2 clk clk enabled 1 0 1 clk x 3 4 clk clk enabled 1 1 1 clk x 4 5 clk clk enabled table 4: function table (controls) control pin 0 1 test pll enabled pll bypassed (static test mode) mr reset (internal logic and pll) normal operation mode oe outputs disabled (q x = l, q x = h), except qfb, qfb outputs enabled vco_sel high frequency operation (vco frequency range from 600 to 1150 mhz) low frequency operation (vco frequency range from 300 to 575 mhz) figure 4. qsync phase relation diagram the mpc9990 qsync output is designed for system syn- chronization purpose. the output frequency relationship be- tween the qa?bank and the qfb?output (see table 3) controls the status of qsync. the internal qsync pulse circuitry is enabled if the frequency relationship between the qa?banks and qfb is not an integer multiple of each other (fqa:fqfb = 1:2, 3:4 and 4:5) (see table 3). qsync is asserted (logic high pulse) centered on coincident rising edges at the qa?bank outputs and qfb. the qsync output transitions at the falling edges of qfb (assertion at the last falling edge of qfb prior to the coincident edge event, deassertion at the next falling edge of qfb). the qsync output pulse width is equal to period of the qfb output (see figure 4, also see the max. skew specifi- cation qfb to qsync). if bsel=1 and the pll is frequency and phase locked, qsync output pulses occur centered on coincident edges be- tween the qa?bank and qb?bank outputs (offset by the feed- back path delay) due to the fixed relationship between clk, qfb and qb bank outputs. table 5: absolute maximum ratings* symbol characteristics min max units condition v cca analog power supply ?0.5 3.6 v v cc core power supply ?0.5 3.6 v v cco output power supply ?0.5 3.6 v v in input voltage ?0.5 v cc + 0.3 v i in input current ?1.0 1.0 ma dc i out output current ?50 50 ma dc t s storage temperature ?50 150 c * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or condi- tions beyond those indicated may adversel y affect device reliability. functional operation at absolute?maximum?rated conditions is no t implied. 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 291 table 6: dc characteristics (v cc = v cca = 3.3 v 5%, v cco = 1.7 to 2.1v, t a = 0 to 70 c) symbol characteristics 0 c 25 c 70 c unit condition y min typ max min typ max min typ max hstl i/o a v cco output power supply 1.7 1.8 2.1 1.7 1.8 2.1 1.7 1.8 2.1 v in input voltage (fb) -0.3 1.45 -0.3 1.45 -0.3 1.45 v differential v dif differential input voltage b (fb) 0.2 1.75 0.2 1.75 0.2 1.75 v differential v cm common mode input voltage c (fb) 0.64 0.9 0.68 0.9 0.68 1.0 v v oh output high voltage 1.0 v x +0.4 1.4 1.0 v x +0.4 1.4 1.0 v x +0.4 1.4 v v ol output low voltage 0 v x -0.4 0.4 0 v x -0.4 0.4 0 v x -0.4 0.4 v lvpecl i/o v cc power supply voltage (core) 3.135 3.3 3.465 3.135 3.3 3.465 3.135 3.3 3.465 v v cca power supply voltage (pll) 3.135 3.3 3.465 3.135 3.3 3.465 3.135 3.3 3.465 v v pp peak-to-peak input voltage clk, pclk 500 1000 500 1000 500 1000 mv v cmr common mode range d clk, pclk v cc -1.4 v cc - 0.6 v cc -1.4 v cc - 0.6 v cc -1.4 v cc - 0.6 v i ih input high current 150 150 150 a i cc power supply current (core) 141 180 141 180 141 180 ma i cca power supply current (pll) 15 20 15 20 15 20 ma lvcmos inputs v ih input high voltage 2 v cc 2 v cc 2 v cc v v il input low voltage 0 0.8 0 0.8 0 0.8 v i i input current 100 100 100 a a. see ?hstl differential input levels? in figure 5 b. v dif specifies the input differential voltage. c. v cm is the maximum allowable range of v tr - ((v tr - v cp )/2). v tr is true input signal, v cp is its complementary input signal. d. v cmr is the difference from v cc and the crosspoint of the differential input signal. normal operation is obtained when the ?high? input is within the v cmr range and the input swing lies within the v pp specification. e. lvpecl input level specifications will vary 1:1 with v cc . figure 5. hstl differential input levels figure 6. hstl output termination and ac test reference ? ? ? ? 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 292 table 7: ac characteristics (v cci = v cca = 3.3 v 5%, v cco = 1.7 to 2.1 v, t a = 0 to 70 c) a symbol characteristics 0 c 25 c 70 c unit condition y min typ max min typ max min typ max f in input frequency b for vco_sel = 0 (high range) 1:1 ratio, asel=00 1:2 ratio, asel=01 3:4 ratio, asel=10 4:5 ratio, asel=11 input frequency b for vco_sel = 1 (low range) 1:1 ratio, asel=00 1:2 ratio, asel=01 3:4 ratio, asel=10 4:5 ratio, asel=11 150.0 150.0 200.0 150.0 75.0 75.0 100.0 75.0 287.5 287.5 287.5 287.5 143.75 143.75 191.67 143.75 150.0 150.0 200.0 150.0 75.0 75.0 100.0 75.0 287.5 287.5 287.5 287.5 150.0 150.0 191.6 150.0 150.0 150.0 200.0 150.0 75.0 75.0 100.0 75.0 287.5 287.5 287.5 287.5 150.0 150.0 191.6 150.0 mhz mhz mhz mhz mhz mhz mhz mhz 600 < f vco < 1150 mhz 300 < f vco < 575 mhz f vco vco frequency vco_sel = 0 (high range) vco_sel = 1 (low range) 600 300 1150 575 600 300 1150 575 600 300 1150 575 mhz mhz f out output frequency c 287.5 287.5 287.5 mhz spo static phase offset, t pd between clk and fb vco_sel=0 vco_sel=1 -200 -250 -50 -50 -200 -250 -50 -50 -200 -250 -50 -50 ps ps dc output duty cycle 45 50 55 45 50 55 45 50 55 % t sk differential output skew t sk(ob) within bank d t sk(o) single frequency e t sk(o) multiple frequency f t sk(ofb) qfb to qa0-6 for asel=00 for asel=01 for asel=10 for asel=11 t sk(o) qfb to qsync 85 25 135 65 ?500 80 100 250 -115 -175 -115 -135 500 85 25 135 65 ?500 80 100 250 -115 -175 -115 -135 500 85 25 135 65 ?500 80 100 250 -115 -175 -115 -135 500 ps ps ps ps ps ps ps ps diff. hstl outputs v pp g minimum input swing 0.5 1 0.5 1 0.5 1 v lvpecl v cmr common mode range 1 v cc -0. 4 1 v cc -0 .4 1 v cc -0 .4 v lvpecl v dif,out minimum output swing 0.6 0.8 0.6 0.8 0.6 0.8 v hstl v x differential output crosspoint voltage 0.64 0.9 0.68 0.9 0.68 1.0 v hstl t jit(cc) cycle-to-cycle jitter f vco >= 750 mhz f vco < 750 mhz 75 125 75 125 75 125 ps ps t jit(per) period jitter vco_sel=0 vco_sel=1 75 125 75 125 75 125 ps ps t jit(io) i/o phase jitter rms (1 ) 600 mhz< f vco <750 mhz 750 mhz< f vco <900 mhz 900 mhz< f vco <1150 mhz 50 40 30 50 40 30 50 40 30 ps ps ps bw pll bandwidth 1:1 ratio, asel=00 1:2 ratio, asel=01 3:4 ratio, asel=10 4:5 ratio, asel=11 0.6-1.0 0.6-1.0 1.0-1.2 0.6-1.0 0.6-1.0 0.6-1.0 1.0-1.2 0.6-1.0 0.6-1.0 0.6-1.0 1.0-1.2 0.6-1.0 mhz mhz mhz mhz t r , t f output transition rate 0.8 2 0.8 2 0.8 2 v/ns t lock pll lock time 10 10 10 ms a. refer to ?hstl output termination and ac test reference? for ac test conditions in figure 6 b. the input frequency for the output configurations are limited by the vco frequency range and the feedback divider. c. f out at which output-to-output skew, v x and dc specification are still meet. f out is primary a function of f in and the input-to-output fre- quency ratio (m:n). d. output skew within bank a outputs (qa0-qa6) and output skew within bank b outputs (qb0-qb2). e. output skew within all outputs (qa0-qa6, qb0-qb2) running at the same output frequency. f. output skew within all outputs (qa0-qa6, qb0-qb2) running at any output frequency. g. v pp specifies the minimum input differential voltage required for switching. 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 293 applications information using the mpc9990 in zero-delay applications nested clock trees are typical applications for the mpc9990 designs using the mpc9990 as pll fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from static fanout buffers. the external feedback option of the mpc9990 clock driver allows for its use as a zero delay buffer. by using the differential qfb output pair as a feedback to the pll the propagation delay through the device is virtually eliminated. the pll aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. the maxi- mum insertion delay of the device in zero-delay applications is measured between the reference clock input (clk) and any output. this effective delay consists of the static phase offset (spo), i/o jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. calculation of part-to-part skew the mpc9990 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. if the reference clock inputs of two or more mpc9990 are connected together, the maximum overall timing uncertainty from the common clk input to any output is: t sk(pp) = t ( ? ) + t sk(o) + t pd, line(fb) + t jit(per) + t jit( ? ) cf this maximum timing uncertainty consist of 4 components: static phase offset (spo), output skew, feedback board trace delay and i/o phase and period jitter. the output skew (t sk(o) ) specification of the mpc9990 is different for single or for dual frequency bank configurations. : figure 7. mpc9990 max. device-to-device skew ? t ? ? ? t due to the statistical nature of i/o jitter a rms value (1 ) is specified. i/o jitter numbers for other confidence factors (cf) can be derived from table 8. table 8: confidence facter cf cf probability of clock edge within the distribution 1 0.68268948 2 0.95449988 3 0.99730007 4 0.99993663 5 0.99999943 6 0.99999999 the feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. in the following example calculation a i/o jitter confi- dence factor of 99.7% ( 3 ) and single frequency configura- tion is assumed, resulting in a worst case timing uncertainty from input to any output of -495 ps to +245 ps relative to clk. t sk(pp) = [?200ps...?50ps] + [?100ps...100ps] + [?75ps...75ps] + [(30ps ?3)...(30ps 3)] + t pd, line(fb) t sk(pp) = [?495ps...+245ps] + t pd, line(fb) due to the frequency dependence of the i/o jitter, figure 8 ?max. i/o jitter versus frequency? can be used for a more pre- cise timing performance analysis. the number for the i/o jitter at a specific frequency can be substituted for the more general datasheet specification number: figure 8. max. i/o jitter versus frequency 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 294 power supply filtering the mpc9990 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply. random noise on the v cca power supply impacts the device ac characteristics, for instance i/o jitter. the mpc9990 provides separate power supplies for the output buffers (v cco ) and the phase-locked loop (v cca ) of the device. figure 9. recommended power supply filter r f 9 for v cc = 3.3v 2 7 the purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive in- ternal analog phase-locked loop. in a digital system environ- ment where it is difficult to minimize noise on the power sup- plies a second level of isolation may be required. a simple but effective form of isolation is a power supply filter on the v cca pin for the mpc9990. figure 9 illustrates a recommended pow- er supply low-pass frequency filter scheme. the mpc9990 vco frequency and phase stability is most susceptible to noise with spectral content in the 300 khz to 3 mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop across the series filter resistor r f . the maximum voltage drop on v cca that can be tolerated is 135 mv with respect to v cc = 3.3v 5%, resulting in a lowest allowable supply voltage for v cca equal to 2.835 v. from the data sheet the i cca current (the current sourced through the v cca pin) is typically 11 ma (15 ma maximum), assuming that the minimum of 3.0v (v cc =3.3v-5%-0.135v) must be maintained on the v cca pin. the resistor r f shown in figure 9 ?recommended power supply filter? should have a maximum resistance of 9 to meet the voltage drop criteria. the minimum resistance for r f and the filter capacitor c f are defined by the required filter characteristics: the rc filter should provide an attenuation greater 40 db for noise whose spectral content is above 300 khz. in the example rc filter shown in figure 9 ?recommended power supply filter?, the filter cut-off frequency is 16.3 khz and the noise attenuation at 300 khz is approximately 42 db. as the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown (6.8 f || 10 nf) ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. although the mpc9990 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds, internal voltage regulation and fully differential pll) there still may be applica- tions in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate pow- er supply noise related problems in most designs. recommended power-up sequence the mpc9990 does not require any special supply ramp sequence in case the system prorides all supply voltages (3.3v and 1.8v) at the same time. the reference clock signal (clk, clk ) can be applied any time during or after the power up sequence if v in is smaller or equal v cc during the voltage transition. following are guidelines for the mpc9990 power-up sequence in case the 3.3v and 1.8v voltage supply cannot be applied at the same time: ? hstl output supply voltage v cco must be powered up to the specified voltage range before or at the same time as v cc . v cca can be powered up before, at the same time or after v cc and v cco . ? at the time the power supplies are powered up, the device should be reset (mr =0). ? apply the clock input signals to the pll (clk, clk ) after all power supplies are stable. then, mr can be deasserted (mr =1). this will release the internal pll which will attempt to lock. ? the time from mr deassertion to pll lock will be specified by the pll lock time t lock. after the pll achieved lock, the ac characteristics are valid. ? outputs can be enabled by oe any time. qfb is not af fected by oe and the pll can achieve lock even if oe is tied high (oe = 1, disable). 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 295 calculating the power consumption the total power dissipated in the mpc9990 (p tot ) can be represented by this formula: p tot = p core + (n ? p output ) where p core is the core and pll power consumption (v cc and v cca pins), p output is the power consumption of the out- put drivers (v cco pins) and n is the number of terminated out- puts: p core = v cc ? i cc p output = (v cco - v out ) ? [(v x - v tt ) r term ] i cc is the current consumption of the core including the cur- rent consumption of the pll. v x represents the average output voltage for a 50% duty cycle output signal. v x and i cc can be obtained from the specification values. v cc , v cco , and the termination resistor r term are application-dependent. table 9: example calculation term value (worst case) value (typical case) v cc 3.3v+5% 3.3v i cc a 180 ma 141 ma p core 624 mw 465 mw v cco 2.1v 1.8v v out b 0.68v 0.8v v x 0.9v 0.8v v tt 0v 0v r term 50 ? 50 ? p output 25.5 mw 16 mw n 24 24 p tot 1237 mw 849 mw a. i cc already includes i cca . b. the value for v out is average output voltage assuming the duty cycle of the output is approx. 50%. 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mpc9990 motorola advanced clock drivers device data 296 figure 10. output?to?output skew t sk(o) , t sk(ob) figure 11. propagation delay (t ? , static phase offset, spo) test reference figure 12. output duty cycle (dc) figure 13. i/o jitter ? ?? figure 14. cycle?to?cycle jitter figure 15. period jitter figure 16. output transition time test reference 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
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